This application claims priority under 35 U.S.C. xc2xa7xc2xa7119 and/or 365 to 9803485-3 filed in Sweden on Oct. 13, 1998; the entire content of which is hereby incorporated by reference.
The present invention relates to a method for interconnecting radio frequency power SiC field effect transistors, a device comprising an interconnect design for frequency power SiC field effect transistors and a radio frequency power SiC field effect transistor with the interconnect design.
Silicon carbide (SiC) transistors have started to be alternatives to both Si and GaAs transistors for power generation at GHz frequencies. They have been predicted and also shown experimentally to handle much higher power density in comparison to the other mentioned transistor types, i.e. the same size transistors can generate several times higher power, depending of the superior material properties. In order to fully utilise the advantages of the SiC dies in a real transistor package, the connection of the die to the package should also be modified. With a conventional MESFET design, featuring interdigitated gate and source bonding pads 1, 2 and wires 3, 4 as shown in FIG. 1, the parasitic inductance from the bonding wires 3, 4 will be much higher for SiC transistor than for the other material types, since the smaller die will allow fewer bonding leads. Especially the parasitic source inductance is deleterious for the transistor characteristics.
A new way to improve the parasitic source inductance is to take advantage of the small size of the transistors and place the bonding pads on both sides of the die in such a way that most of the source bonding wires will go perpendicularly to the gate and drain bonding wires. Multiple bonding wires can be connected to the source bonding pads, reducing the source inductance. An additional advantage comes from such arrangement by reducing the mutual inductance between source/gate and between source/drain due to orthogonal wire placement.
In a case when multiple transistor dies have to be placed in the same package, a jumper chip can be placed between the dies, to simplify bonding procedure and further reducing the source inductance.
The invention will be further described with reference to preferred embodiments and enclosed drawings.